Index Registers and Loops
Index registers on the 7090/94 were 15-bits in length (enough to span 32,768 words) and were used primarily for loop counters and to modify addresses.
Almost all instructions could specify an index register the identity of which was coded into the tag field of the instruction in bits 18-20. The three bits could code up to seven registers -- XR1, XR2,..., XR7 on the 7094 but only XR1, XR2, and XR4 on the 7090.
Symbolic coding of index registers used a '1' through '7' following an address (separated by a comma). As example, an ADD instruction to add the contents of the location named DATA to the AC using index register modification with XR4 was coded as:
ADD DATA, 4
Index registers had four specific associated instruction types: Load an index register; store the contents of an index register; increase or decrease the contents of an index register; and test the contents of an index register.
When an instruction was coded to be modified by the contents of an index register, the contents of the register were subtracted from the address portion of the instruction (bits 21-35). The contents of the index register could be added to the address field to form the final address by specifying the 2's-complement of the quantity in the source code which would also be subtracted to yield the same affect as adding (almost all of the remainder of the 7090/94 architecture was 1's-complement based). Therefore, addresses could be modified either upward or downward.
The index register specific instructions were of type 'A' (see Instruction Formats for details of type 'A' instructions). As can be seen from the following table, 18-instructions loaded and stored values to and from the index registers. Index registers could be loaded from or stored into either the decrement or address field of either the AC register or a memory location. In all cases, the 2's-complement could be loaded or stored instead of the number (e.g., AXC -15,4 loaded XR4 with the 2's-complement of 15: 000000000001111 -> 15 (decimal); 111111111110000 -> 1's-complement; 111111111110001 -> 2's-complement).
Instructions for Loading and Storing Index Registers
* - Address portion of these instructions not used.
|SOURCE||Y-Address (Bits 21-35)||2's-COMPLEMENT OF (Bits 21-35)||DECREMENT (Bits 3-17)||2's-COMPLEMENT (Bits 3-17)|
|LOAD INDEX FROM STORAGE LOCATION:||'LXA' (Load Index from Address)||'LAC' (Load Complement of Address into Index)||'LXD' (Load Index from Decrement)||'LDC' (Load Complement of Decrement in Index)|
|LOAD INDEX FROM AC REGISTER:*||'PAX' (Place Address in Index)||'PAC' (Place Complement of Address in Index||'PDX' (Place Decrement in Index)||'PDC' (Place Complement of Decrement in Index)|
|LOAD INDEX FROM INSTRUCTION:||'AXT' (Address to Index True||'AXC' (Address to Index Complemented)|
|STORE INDEX INTO STORAGE LOCATION:||'SXA' (Store Index into Address||'SCA'** (Store Complement of Index into Address)||'SXD' (Store Index into Decrement)||'SCD'** (Store Complement of Index Decrement)|
|STORE INDEX INTO AC REGISTER:*||'PXA' (Place Index in Address)||'PCA'** (Place Complement of Index in Address)||'PXD' (Place Index in Decrement)||'PCD'** (Place Complement of Index in Decrement)|
** - 7094 Only
There were five instructions that incremented, decremented, and tested the contents of index registers (all type 'A' formats). Four of the instructions had a conditional transfer to the Y-address and one had an unconditional transfer.
Instructions for Incrementing, Decrementing, and Testing Index Registers
|'TXI' (Transfer with Index Incremented)||The decrement was added to the specified index register and the next instruction was taken from the Y-address|
|'TXH" (Transfer on Index High)||If the contents of the specified index register were greater than the decrement field, then the next instruction was at Y; else the next sequential instruction was executed.|
|'TXL' (Transfer on Index Low or Equal)||Reverse of 'TXH' -- Caused a transfer if the index register contents were less than or equal to the contents of the decrement field.|
|'TIX' (Transfer on Index)||If the contents of the specified index register were greater than the contents of the decrement field, then the number in the index register was reduced by the contents of the 'D' field and the next instruction was at 'Y'. If the contents of the index register were less than or equal to, then no decrementing of the index register occurred and the next sequential instruction was executed,|
|'TNX' (Transfer on No Index)|| Same as 'TIX' except that the transfer conditions were reversed -- If the contents of the specified index register were less than or equal to the 'D' field, then the next instruction was at 'Y'. The decrement still occurred only if the index register contents were greater than the contents of the 'D' field.|
The symbolic coding specified the decrement field as the field following the index register tag field and was separated by a comma:
TXH NEXT, 2, -50 IF XR2 > -50, JUMP TO 'NEXT'
Index registers could be used for loop counting either by counting down or by counting up. Due to the 'TIX' instruction, counting down, in general, required one less instruction than counting up. The increment or decrement could be any size but was, of course, limited to 15-bits.
The following example compares the increment and decrement loop logics (loop 300 times):
INCREMENT LOGIC DECREMENT LOGIC
An example of using an index register to sum 300 numbers located at DATA into SUM is as follows:
AXT 1, 2 AXT 300, 2
LOOP ... LOOP ...
TXI NEXT, 2, 1 TXI LOOP, 2, 1
NEXT TXL LOOP, 2, 300
Almost all instructions could be modified by an index register -- for example, tagging 'TRA' (Unconditional Transfer) changed it to a Computed GOTO or Case (in more or less modern parlance) as the transfer depended on the contents of an index register.
AXT 298, 3 INITIALIZE XR3 AS COUNTER AND AS OFFSET
CLA DATA GET FIRST NUMBER INTO AC...
LOOP ADD DATA+299, 3 ADD IN NEXT NUMBER...
TOV ERROR CHECK FOR OVERFLOW -> ERROR...
TIX LOOP, 3, 1 TEST AND DECREMENT XR3...
STO SUM HANG ONTO RESULT
DATA BSS 300 LOTZA NUMBERS...
http://www.frobenius.com/Index-Registers.htm -- Last Revision: 23 August 2001
Copyright © 1996 - 2018 Jack Harper (unless otherwise noted)