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IBM 7090/94 Instruction Set
(Index)

An Instruction Word for the 7090/94 consisted of 35 bits and a sign for a total of 36-bits. The instruction was divided into fields, each of which was named and specified specific information.

There were five major grouping of instructions that were referred to as Type A, B, C, D, and E (Press Here to see the different formats in more detail).

The following fields were defined: The symbol <- denotes is replaced with.

The Double Precision floating point instructions, for the 7094, were the same as Single Precision floating point instructions except for a leading D. They are, otherwise, not documented here.

INDEX TO INSTRUCTIONS
ACLADDADMALSANAANSARSAXCAXT
BSFiBSRiBTTi
CALCAQCASCHSCLACLMCLSCOMCRQCVR
DCTDFADDFAMDFDHDFDPDFMPDFRNDFSBDFSMDUFADUFMDUFSDVHDVP
ECTMEFTMEMTMENBENKERAESNTESTMETMETTi
FADFAMFDHFDPFMPFRNFSBFSM
HPRHTR
IIAIILIIRIISIOxy(N)IOT
LACLASLBTLCHiLDCLDILDQLFTLFTMLGLLGRLLSLMTMLNTLRSLSNM
LTMLXALXD
MPRMPYMSE
NOPNZT
OAIOFTONTORAORSOSI
PACPAIPAXPBTPCAPCDPDCPDXPIAPSEPXAPXD
RCDiRCHiRCTRDCiRDSREWiRFTRIARICiRILRIRRISRNDRNTRPRiRQL
RSCiRTBiRTDiRUNi
SBMSCASCDSCHiSDHiSDLiSILSIRSLFSLNSLQSLTSLWSPRiSPTiSPUi
SSMSSPSTASTCiSTDSTISTLSTOSTPSTQSTRSTTSTZSUBSWT
SXASXD
TCNiTCOiTEFiTIFTIOTIXTLQTMITNOTNXTNZTOVTPLTQOTQPTRA
TRCiTSXTTRTXHTXITXLTZE
UAMUFAUFMUFSUSM
VDHVDPVLM
WEFiWPBiWPDiWPUiWRSWTBiWTDi
XCAXCLXEC
ZET



7090/94 INSTRUCTIONS

ACL
'Add and Carry Logical Word'+0361
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) + c(Y)

The 'ACL' instruction operates on a 36-bit word. The sign position is treated as an additional bit position. When using the AC register, the P position is used instead of the S position for the algebraic sign. 'ACL' adds the c(Y) to the c(AC), bits P, 1-35. If an overflow occurs, then the bit is added to the bit-35 in an end-around carry. (Index)



ADD
"Add"+0400
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) + c(Y).

The c(Y) are added algebraically to the c(AC) and the result is placed into the AC. The c(Y) remain unchanged. Numbers of the same magnitude, but with different signs (e.g., +2, -2) will result in zero with the original sign of the AC. (Index)



ADM
'Add Magnitude'+0401
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) + Magnitude( c(Y) )

The absolute magnitude of the c(Y) are added to the c(AC). (Index)



ALS
'Accumulator Left Shift'+0767
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC)[Shifted Left]

The c(AC) are shifted left by the number of bits specified in positions 28-35 of the address portion (Y) of the instruction. Vacated positions are automatically zero-filled. The AC will be completely cleared if the specified shift is larger than the size of the AC. (Index)



ANA
'AND to Accumulator'-0320
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) AND c(Y)

Each bit of the c(Y) is logically ANDed with the corresponding bit in the c(AC) and then stored in the corresponding bit of the c(AC). AC positions S and Q are set to bit zero. (Index)



ANS
'AND to Storage'+0320
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(Y) AND c(AC)

Each bit of the c(AC), positions P, 1-35, is logically ANDed with the corresponding bit in the c(Y) and the result is then placed in the c(Y). (Index)



ARS
'Accumulator Right Shift'+0071
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) [Right Shifted]

The c(AC) are logically shifted to the right by the number of bits specified in positions 28-35 of the address (Y) portion of the instruction. Vacated bit positions are automatically zeroed. The contents of the AC will be cleared if the instruction calls to shift more bits than the size of the AC. (Index)



AXC
'Address to Index Complemented'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(Instruction Word) [2s Complement of Bits 21-35]

The contents of the specified Index Register are replaced with the 2s-complement of the Y field, bits 21-35, of the instruction word. (Index)



AXT
'Address to Index True'+0774
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- Y [Positions 21-35 only]

The contents of the Y-field of the instruction, positions 21-35, replace the contents of the specified Index Register. (Index)



BSFi
'Backspace File'-0764
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

The tape, designated by Y, moves backward until and end-of-file or load point is encountered. (Index)



BSRi
'Backspace Record'+0764
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Causes the tape, specified in the Y-field, to back up until an end-of-record gap or load point is reached. The primary purpose of the 'BSR' instruction is for tape-error routines. (Index)



BTTi
'Beginning of Tape Test'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes [TAG]Indirection: No
Description:c(IC) <- c(IC) + 1 or c(IC) + 2

The Channel ('A' - 'H') must be specified (e.g., 'BTTA'). If a tape is given a backspace ('BSR') while at the load point position, then an indicator is automatically turned on. If the indicator is ON, then the 'BTTi' instruction turns the indicator OFF and the machine executes the next sequential instruction. If the indicator is OFF, the the 'BTTi' instruction causes the machine to skip one instruction. (Index)



CAL
'Clear and Add Logical Word'-0500
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- (Y)

The c(AC) are replaced with the contents of the specified (Y). However, the P position of the AC is replaced with the sign of the (Y). The instruction is identical to 'CLA" with exception of the sign bit. (Index)



CAQ
'Convert by Addition from MQ'-0114
Type C: [OP CODE: S, 1-9] [C: 10-17] [Unused: 18-19] [20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

The 'CAQ' instruction is used to convert information in one form to another form at high speed and treats each 36-bit word as a set of 6-bit bytes and operates on each byte in sequence.

The MQ is considered to consist of six 7-bit bytes that are designated as follows: L1: Bits S and 1-5; L2: Bits 6-11;, ..., L6: Bits 30-35. An effective address Y + L1 is formed and the c(Y + L1) are added to the c(AC) (Q, P, 1-35 with the sign left unchanged). Then the c(MQ) is rotated six bits to the left. As a next step, a new effective address Y + L2 is formed, where Y = c(Y + L1) (bits 21-35), and the c(Y + L2) are added to the AC. Then the MQ is rotated six more bits to the left. This process occurs N times where N is specified in the C field (10-17) of the instruction. (Index)



CAS
'Compare AC with Storage'+0340
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(IC) + 2 or c(IC) + 3

The 'CAS' instruction provides a three-way transfer that depends on the c(AC) and the c(Y). (1) If the c(AC) are algebraically greater than the c(Y), then the machine executes the next sequential instruction. (2) If the c(AC) are algebraically equal to the c(Y), then the machine skips one instruction. (3) If the c(AC) are algebraically less than the c(Y), then the machine skips two instructions. (Index)



CHS
'Change Sign'+0760/2
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description: c(AC) <- c(AC) [Sign Bit Flipped]

The Sign bit of the c(AC) is changed from a one to a zero or from a zero to a one. (Index)



CLA
"Clear and Add"+0500
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(Y). AC(q) <- 0. AC(p) <- 0.

Replace the c(AC) with the c(Y). The Q and P bit-positions in the AC are zeroed and the c(Y) are unchanged. (Index)



CLM
'Clear Magnitude'+0760/0
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [VALUE: 24-35]
Indexing: Yes -- But may change the operation [TAG]Indirection: No
Description: c(AC) <- 0 [Sign Left Unmodified]

The c(AC) (bits Q, P, 1-35) are cleared and the sign bit (S) is left unchanged. (Index)



CLS
'Clear and Subtract'+0502
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- -c(Y)

The c(AC) are replaced with the negative of the c(Y). (Index)



COM
'Complement Magnitude'+0760/6
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [VALUE: 24-35]
Indexing: Yes -- But may change operation [TAG]Indirection: No
Description: c(AC) <- Complement( c(AC) ) [S Left Unchanged]

All binary ones are replaced with binary zeros and all binary zeros are replaced with binary ones in the c(AC) in the Q, P, 1-35 bit positions. The sign bit (S) is left unchanged. (Index)



CRQ
'Convert by Replacement from MQ'-0154
Type C: [OP CODE: S, 1-9] [C: 10-17] [Unused: 18-19] [20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

The 'CRQ' instruction is used to convert information in one form to another form at high speed and treats each 36-bit word as a set of 6-bit bytes and operates on each byte in sequence.

The MQ is considered to consist of six 7-bit bytes that are designated as follows: L1: Bits S and 1-5; L2: Bits 6-11;, ..., L6: Bits 30-35. An effective address Y + L1 is formed and the c(Y + L1) replace L1 of the c(MQ). Then the c(MQ) is rotated six bits to the left. As a next step, a new effective address Y + L2 is formed, where Y = c(Y + L1) (bits 21-35), and the c(Y + L2) replace L2 of the c(MQ). Then the MQ is rotated six more bits to the left. This process occurs N times where N is specified in the C field (10-17) of the instruction. (Index)



CVR
'Convert by Replacement from AC'+?
Type C: [S, 1-10] [C: 10-17] [Tag: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Details not Known (Index)



DCT
'Divide Check Test'+0760 0012
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-22] [OP CODE: 23-35]
Indexing: NoIndirection: No
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

If the Indicator is ON, then it is turned OFF and the machine executes the next sequential instruction. If the Indicator is OFF, then the next instruction is skipped and the machine executes the following instruction. (Index)



DFAD
'Double Precision Floating Point Add'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details Not Known (Index)



DFAM
'Double Precision Floating Point Add Magnitude'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details Not Known (Index)



DFDH
'Double Precision Floating Point Divide or Halt'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details Not Known (Index)



DFDP
'Double Precision Floating Point Divide or Proceed'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Unknown (Index)



DFMP
'Double Precision Floating Point Multiply'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



DFRN
'Double Precision Floating Point Round'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change of operation [TAG]Indirection: No
Description:

(Index)



DFSB
'Double Precision Floating Point Subtract'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



DFSM
'Double Precision Floating Point Subtract Magnitude'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



DUFA
'Double Precision Floating Point Unnormalized Add'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



DUFM
'Double Precision Floating Point Unnormalized Multiply'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



DUFS
'Double Precision Floating Point Unnormalized Subtract'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



DVH
"Divide or Halt"+0220
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC-MQ) <- c(AC-MQ) / c(Y)

The c(AC-MQ) are divided algebraically by the c(Y). The quotient replaces the c(MQ) and the remainder replaces the c(AC). If division cannot complete (divide by zero), then the machine halts and the "Divide-Check" indicator light illuminates on the control console. The dividend must be placed into the AC-MQ prior to executing the DVH. If it occupies only one register, then the other must be first cleared -- the sign of the AC should be made to agree with the sign of the MQ to assure that algebraic division will occur if the dividend is negative (a Long Left Shift of zero can be used) (Index)



DVP
'Divide or Proceed+0221
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC-MQ) <- c(AC-MQ) / c(Y)

The c(AC-MQ) are divided algebraically by the c(Y). The quotient replaces the c(MQ) and the remainder replaces the c(AC). If division cannot complete (divide by zero), then the "Divide-Check" indicator light illuminates on the control console and the machine continues to execute the next sequential instruction (instead of halting like the 'DVH' instruction). The dividend must be placed into the AC-MQ prior to executing the DVP. If it occupies only one register, then the other must be first cleared -- the sign of the AC should be made to agree with the sign of the MQ to assure that algebraic division will occur if the dividend is negative (a Long Left Shift of zero can be used) (Index)



ECTM
'Enter Copy Trap Mode'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description:

Details not Known -- See section on Trapping for more details. (Index)



EFTM
'Enter Floating Trap Mode'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description:

Details not Known -- See section on Trapping for more details. (Index)



EMTM
'Enter Multiple Tag Mode'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description:

(Index)



ENB
'Enable from Y'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



ENK
'Enter Keys'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes -- But may cause change in operation [TAG]Indirection: No
Description: c(MQ) <- c(Switch Register)

Replaces the c(MQ) with the contents of the 36 control console switches. An UP position for a switch results in binary zero and a DOWN position results in binary one. There is no operand address, but the positions 33-35 must contain octal 100. (Index)



ERA
'Exclusive OR to Accumulator'+0322
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) XOR c(Y)

Each bit of the c(Y) is exclusive ORed with the corresponding bit in the c(AC), positions P, 1-35, and then placed in the corresponding bit in the c(AC). The c(Y) and the S and Q positions of the AC remain unchanged. The sign of Y will be in the P position in the AC. (Index)



ESNT
'Enter Storage Nullification and Transfer'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



ESTM
'Enter Select Trap Mode'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description:

Details not Known (Index)



ETM
'Enter Trapping Mode'+0760/0007
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [OP CODE: 24-35]
Indexing: Yes -- But may change Instruction [TAG]Indirection: No
Description:

Causes the machine to enter the Transfer Trapping Mode whereby any transfer forces the machine to automatically transfer to location 0001.

For example, when in Transfer Trapping Mode, a standard 'TZE' (Transfer on Zero) instruction, which if the c(AC) are zero, should transfer to (Y), will instead, automatically transfer to location 0001.

The 'TRA' (Transfer) instruction, when in Transfer Trapping Mode, will always instead transfer to location 0001.

The primary use of the Transfer Trap Mode is to check and debug a program. When operating in the mode, the location of every transfer instruction (with exception of the special Trap Transfer instruction), replaces the address part of location 0000. This replacement occurs whether the condition, if any, for transfer occurs or not. A special Trap Trace program may be written, starting at location 0001, that will write out (to a special tape) all transfer instructions for off-line printing. At the end of the trace program, control is returned to the main program which will continue until another transfer instruction returns it to the trace program. When the information accumulated by the trap trace program is printed, it gives the programmer a record of the registers at each transfer instruction that provide the conditions for transfer. When the software has been debugged, then the Enter Trapping Mode can be replaced with a NOP.

The 'ETM' instruction, when executed, turns on the Trapping Indicator and the Trap Light on the control console. The machine will continue to operate in the trapping mode until a 'Leave Trapping Mode' instruction is executed or until the Clear or Reset keys are pressed on the console. (Index)



ETTi
'End of Tape Test'-0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

The Channel ('A' - 'H') must be specified (e.g., 'ETTA'). If an end of tape condition occurs while writing to tape, then an indicator is automatically turned ON. If the indicator is ON, then the 'ETTi' instruction turns it OFF and the machine executes the next sequential instruction. If the indicator is OFF, then the machine skips one instruction. (Index)



FAD
'Floating ADD'+0300
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) * c(Y)

The floating point number in Y is added algebraically to the floating point number in the AC. The most significant portion of the result is placed in the AC as a normalized floating point number and the least significant portion of the result is placed in the MQ as a floating point number with a characteristic 33 less than the AC characteristic. The C(Y) are not changed. The sign in both the AC and in the MQ will be that of the result. (Index)



FAM
'Floating Add Magnitude'+0304
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) + c(Y)

The absolute value of the floating point number in the c(Y) are added to the floating point number in the c(AC) and the normalized floating point result is placed into the c(AC and MQ) (Index)



FDH
'Floating Divide or Halt'+0240
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) / c(Y)

The floating point number in the AC is algebraically divided by the floating point number in Y. The floating point quotient will be placed in the MQ and the floating point remainder will be placed in the AC. If the fractional portion of the floating point number in the AC is equal to or greater than twice the fractional portion of the floating point number in the Y -- which can only happen if one or more of the numbers are unnormalized -- or if Y contains floating point zero, then the Divide Check Indicator is illuminated on the control console and the machine will halt. If both the dividend and divisor are normalized floating point numbers, then the quotient will also be normalized. (Index)



FDP
'Floating Divide or Proceed'+0241
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) / c(Y)

The floating point number in the AC is algebraically divided by the floating point number in Y. The floating point quotient will be placed in the MQ and the floating point remainder will be placed in the AC. If the fractional portion of the floating point number in the AC is equal to or greater than twice the fractional portion of the floating point number in the Y -- which can only happen if one or more of the numbers are unnormalized -- or if Y contains floating point zero, then the Divide Check Indicator is illuminated on the control console and the machine continues to the next sequential instruction. If both the dividend and divisor are normalized floating point numbers, then the quotient will also be normalized. (Index)



FMP
'Floating Multiply'+0260
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(MQ) * c(Y)

The floating point number in Y is algebraically multiplied by the floating point number in MQ. The most significant portion of the product is placed in the AC and the least significant portion is placed in the MQ. If either of the numbers are not normalized, then the product may or may not be normalized. The c(Y) are not changed. (Index)



FRN
'Floating Round'+0760/Binary 11 in Bits-34/35
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - But indexing may change the operation [TAG]Indirection; No
Description: c(AC and MQ) <- c(AC and MQ) [Rounded]

If the c(MQ) are greater than or equal one-half of the 35th bit in the c(AC), then binary one is added to the 35th-bit in the c(AC). (Index)



FSB
'Floating Subtract'+0302
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) - c(Y)

The floating point number in Y is subtracted from the floating point number in AC and the results are placed in the c(AC and MQ) as a normalized floating point number. The most significant part of the fraction is placed in the c(AC). The c(Y) are not modified. (Index)



FSM
'Floating Subtract Magnitude'+0306
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) - c(Y)

The absolute value of the floating point number in the c(Y) are subtracted from the floating point number in the c(AC) and the floating point result is placed in the c(AC and MQ) with the most significant portion of the fraction in the c(AC). (Index)



HPR
'Halt and Proceed'+0420
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

The 'HPR' instruction causes the machine to halt. Pressing the Start key on the control console will cause the machine to resume with the next sequential instruction. (Index)



HTR
"Halt or Transfer"+0000
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

The machine halts. If the operator then presses the START button, then the processor continues by transferring to the (Y) address for its next instruction. If the specified address is the same as that of the HTR instruction, then the machine simply halts again. (Index)



IIA
'Invert Indicators from Accumulator'+0041
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- c(Sense Indicator) XOR c(AC)

Each bit of the Sense Indicator Register is matched with the corresponding bit of the c(AC). Where a bit in the c(AC) is binary one, then the corresponding bit in the Sense Indicator is flipped. The effect is to replace the c(Sense Indicator Register) with the XOR of the c(AC) and the c(Sense Indicator Register). (Index)



IIL
'Invert Indicators of Left Half'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17]] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- c(Sense Indicator) XOR 777777000000

The bits of the left half of the Sense Indicator are flipped. The bits of the right half are not changed. (Index)



IIR
'Invert Indicators of Right Half'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- c(Sense Indicator) XOR 000000777777

The bits of the right half of the Sense Indicator Register are flipped. The bits in the left half are not changed. (Index)



IIS
'Invert Indicators from Storage'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Sense Indicator) <- c(Sense Indicator) XOR c(Y)

Each bit of the Sense Indicator Register is matched with the corresponding bit of (Y). Where a bit in (Y) is binary one, then the corresponding bit in the Sense Indicator is flipped. The effect is to replace the c(Sense Indicator Register) with the XOR of (Y) and the c(Sense Indicator Register). (Index)



IOxy(N)
'Input-Output Channel Command'+????
Type A: [S, 1-2] [DECREMENT: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

...where 'x' is either 'C' for Count Control; 'R' for Record; or 'S' for Signal. 'y' is either 'P' for Proceed; 'T' for Transfer; or 'D' for Disconnect. 'N' is for No Transmission.

For example, 'IOCD' (I/O under Count Control and Disconnect), for input, will read the number of specified words (in the DECREMENT), beginning with the word specified by the ADDRESS. For output, 'IOCD' will write the number of words, specified in the DECREMENT, beginning with the word specified by the ADDRESS and, after completion, will stop the execution of any other Channel Commands.

Another example -- 'IORT' (Input/Output of a Record and Transfer), for input, always disconnects the Channel at the end of a record or when the count in the DECREMENT goes to zero (whichever is first). For output, 'IORT' writes a record, with the number of words specified in the DECREMENT, starting at the word specified in the ADDRESS. (Index)



IOT
'Input-Output Check Test'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description:

Details not Known (Index)



LAC
'Load Complement of Address in Index'+0535
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- 2's Complement of c(Y)

The 2's complement of the c(Y) (bits 21-35) of the instruction word are loaded into the specified Index Register. The c(Y) are left unchanged. (Index)



LAS
'Logical Compare Accumulator with Storage'-0340
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(IC) + 2 or c(IC) + 3

The c(AC), bits Q, P, 1-35, and the c(Y) are compared as unsigned numbers. If the c(AC) are greater than the c(Y), then the machine executes the next sequential instruction. If the c(AC) equal the c(Y), then the machine skips one instruction. If the c(AC) are less than the c(Y), then the machine skips two instructions. (Index)



LBT
'Low-Order Bit Test'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

Details not Known (Index)



LCHi
'Load Channel'+054j (j=4, 7 alternating signs)
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Causes the specified Channel to load another Channel Control Word.

If the Data Channel has been selected and is executing a Channel Command, then the SCHi instruction can be given that forces the Channel to load another Channel Command word. The load channel is not executed unless the current Channel Command is a transfer type. If it is, then the LCHi instruction furnishes the next Channel Command word. The execution of the load command is delayed until a transfer-type channel command is used. If never given, then the instruction becomes a NOP. i specifies the Channel and may be either 'A', 'B', ..., 'H' to designate the channel. See the section on I/O for additional details. (Index)



LDC
'Load Complement of Decrement in Index'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(Y) [2s Complement, Bits 3-17]

The contents of the specified Index Register are replaced with the 2s complement of the contents of the decrement field, bits 3-17, of the c(Y). (Index)



LDI
'Load Indicators'+0441
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Sense Indicator Register) <- c(Y)

The contents of the Sense Indicator Register are replaced with the c(Y). The c(Y) remain unchanged. (Index)



LDQ
"Load MQ Register"+0560
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(MQ) <- c(Y)

The c(Y) replace the c(MQ). The bits at the address (Y) move into the MQ and the c(Y) remain unchanged. (Index)



LFT
'Left Half Indicators OFF Test'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: Details not Known

(Index)



LFTM
'Leave Floating Trap Mode'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

Details not Known (Index)



LGL
'Logical Left Shift'-0763
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC and MQ) [Shifted Left]

The c(AC) and the c(MQ) are treated as one long register including the S, Q, P in the AC and the S in the MQ. The contents are shifted to the left by the number of places specified in positions 28-35 of (Y) -- the address portion of the instruction. The sign of the AC remains unchanged. (Index)



LGR
'Logical Shift Right'-0765
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC and MQ) [Shifted Right]

The c(AC) and the c(MQ) are treated as one long register including the S, Q, P in the AC and the S in the MQ. The contents are shifted to the right by the number of places specified in positions 28-35 of (Y) -- the address portion of the instruction. The sign of the AC remains unchanged. (Index)



LLS
'Long Left Shift'+0763
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c( AC and MQ ) <- c( AC and MQ ) [Shifted Left]

The c(AC), including positions P and Q, and the C(MQ) are treated as one long register. The number of bits to shift left is specified by the number placed in positions 28-35 of the instruction. The sign of the AC is forced to agree with the sign of the MQ. If a non-zero bit is shifted into position P, then the AC Overflow indicator will be illuminated on the control console and any bits shifted past position Q will be lost. (Index)



LMTM
'Leave Multiple Tag Mode'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

Details not Known (Index)



LNT
'Left Half Indicators ON Test'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17]] [R: 18-35]
Indexing: NoIndirection: No
Description: Details not Known

(Index)



LRS
'Long Right Shift'+0765
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c( AC and MQ ) <- c( AC and MQ ) [Shifted Right]

The c(AC), including positions P and Q, and the C(MQ) are treated as one long register. The number of bits to shift right is specified by the number placed in positions 28-35 of the instruction. The sign of the MQ is forced to agree with the sign of the AC and bits shifted past position 35 of the MQ are lost. (Index)



LSNM
'Leave Storage Nullification'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

Details not Known (Index)



LTM
'Leave Trapping Mode'-0760/0007
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [OP CODE: 24-35]
Indexing: Yes -- But may change the Instruction[TAG]Indirection: No
Description:

Turns OFF the Trap Indicator and the Trap Light on the control console. Another 'ETM' instruction is required to place the machine back into the Transfer Trapping Mode. See the 'ETM' (Enter Trapping Mode) instruction for a full description of the Transfer Trapping Mode. (Index)



LXA
'Load Index from Address'+0534
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(Y) [Positions 21-35 only]

The address portion of the c(Y), positions 21-35, replace the contents of the specified Index Register. The c(Y) are not changed. (Index)



LXD
'Load Index from Decrement'-0534
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(Y) [Positions 3-17 only]

The decrement portion of the c(Y), positions 3-17, replace the contents of the specified Index Register. The c(Y) are unchanged. (Index)



MPR
'Multiply and Round'-0200
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) * c(MQ)

The multiplier is first loaded into the MQ. The c(Y) are multiplied by the c(MQ) with the most significant 35-bits placed into the c(AC) and the least significant 35-bits placed into the c(MQ). After completion of the multiplication, the c(AC) are increased by one if the first position of the c(MQ) is a binary one. The rounding that can occur depends on the scaling of the results already present in the AC and MQ registers. The signs of the AC and MQ registers are both the algebraic sign of the product. (Index)



MPY
"Multiply"+0200
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(MQ) * c(Y)

The c(MQ) are multiplied algebraically by the c(Y). The product replaces the c(AC and MQ) with the most significant 35 bits in the AC and the least significant 35 bits in the MQ. Overflow is not possible and the product is positioned to the right with enough leading zeros to completely fill both registers. (Index)



MSE
'Minus Sense'-0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause operation [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

If the Sense Switch, on the control console, indicated by the contents of the Y field (bits 24-35) of the instruction word (1, 2, ..., 6) is ON, then the next sequential instruction is skipped. If the light indicated is OFF, then the machine executes the next sequential instruction. (Index)



NOP
'No Operation'+0761
Type D: [OP CODE: S, 1-11] [Unused: 12-35]
Indexing: NoIndirection: No
Description: c(IC) <- c(IC) + 1

Causes no action by the machine. The computer executes the next sequential instruction. (Index)



NZT
'Storage Not Zero Test'-0520
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

If the c(Y) are non-zero, then the machine will skip one instruction. If the c(Y) are zero, then the machine executes the next sequential instruction. The c(Y) are not changed. (Index)



OAI
'OR Accumulator to Indicators'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- c(Sense Indicator) OR c(AC)

The c(AC) are logically ORd with the contents of the Sense Indicator and the result is placed into the Sense Indicator). (Index)



OFT
'Off Test for Indicators'+0444
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

For each bit in the c(Y) that is a binary one, the corresponding bit in the Sense Indicator Register is checked. If all of the positions checked, in the Sense Indicator Register, are binary zeros, then the machine skips one instruction. If any of the checked bit positions are binary one, then the machine executes the next sequential instruction. (Index)



ONT
'On Test for Indicators'+0446
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

For each bit in the c(Y) that is a binary one, the corresponding bit in the Sense Indicator Register is checked. If all of the positions checked, in the Sense Indicator Register, are binary ones, then the machine skips one instruction. If any of the checked bit positions are binary zero, then the machine executes the next sequential instruction. (Index)



ORA
'OR to Accumulator'-0501
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) OR c(Y)

Each bit of the c(Y) is logically ORed with the corresponding bit in the c(AC) and then placed in the corresponding bit in the c(AC). The c(Y) and the S and Q positions of the AC remain unchanged. The sign of Y will be in the P position of the AC. (Index)



ORS
'OR to Storage'-0602
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(Y) OR c(AC)

Each bit of the c(Y) is logically ORed with the corresponding bit of the c(AC) and then stored in the corresponding bit of the c(Y). The bit in position P of the AC will be in the sign position of the c(Y). (Index)



OSI
'OR Storage to Indicators'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Sense Indicator) <- c(Sense Indicator) OR c(Y)

The c(Y) are logically ORd with the contents of the Sense Indicator and the result stored in the Sense Indicator. (Index)



PAC
'Place Complement of Address in Index'+0737
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(XR) <- 2's Complement of c(AC)

The 2's complement of the c(AC), bits 21-35, replace the contents of the specified Index Register. The c(AC) are not changed. (Index)



PAI
'Place AC in Indicators'+0044
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator Register) <- c(AC)

The c(AC), positions P and 1-35, replace the contents of the Sense Indicator Register. The c(AC) remain unchanged. (Index)



PAX
'Place Address in Index'+0734
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(AC)

The c(AC), bits 21-35, replace the contents of the specified Index Register. The c(AC) are not changed. (Index)



PBT
'P-Bit Test'-0760/1
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [OP CODE: 24-35]
Indexing: Yes - But may change operation [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

If the c(AC), bit P, is binary one, then the machine skips the next instruction. If the c(AC), bit P, are binary zero, then the machine executes the next sequential instruction. (Index)



PCA
'Place Complement of Index in Address'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(AC) <- c(IR) [2s Complement]

The contents of the AC, bits 21-35, are replaced with the 2s complement of the contents of the specified Index Register. No other bits in the c(AC) are changed. (Index)



PCD
'Place Complement of Index in Decrement'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(AC) <- c(XR) [2s Complement, Bits 3-17 of AC]

The contents of the decrement field, bits 3-17, of the AC, are replaced with the 2s complement of the contents of the specified Index Register. (Index)



PDC
'Place Complement of Index in Decrement'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(AC) [2s Complement, Bits 3-17]

The contents of the specified Index Register are replaced with the 2s complement of the contents of the decrement field, bits 3-17, of the AC. (Index)



PDX
'Place Decrement in Index'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(IR) <- c(AC) [Bits 3-17]

The contents of the specified Index Register are replaced with the contents of the decrement field, bits 3-17, of the c(AC). (Index)



PIA
'Place Indicators in AC'-0046
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(AC) <- c(Sense Indicator Register)

The c(AC), positions P, 1-35, are replaced with the contents of the Sense Indicator Register. Positions S and Q of the AC are cleared and the Sense Indicator remains unchanged. (Index)



PSE
'Plus Sense'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

If the Sense Switch on the control console, indicated by the contents of the Y field (bits 24-35) of the instruction (switch: 1, 6) is OFF, then the next instruction is skipped. If the switch is ON, then the machine executes the next sequential instruction. (Index)



PXA
'Place Index in Address'+0754
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(AC) <- c(XR)

The contents of the specified Index Register replace the c(AC), bits 21-35, and the remainder of the AC is cleared. If the TAG is specified as zero, then the entire contents of the AC are cleared. (Index)



PXD
'Place Index in Decrement'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: The contents of the specified Index Register are placed into the decrement field, bits 3-17, of the c(AC). No other bits in the c(AC) are changed.

(Index)



RCDi
'Read Select Card Reader on Channel i'+0762
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No/th>
Description:

Specific form of the general 'RDS' instruction -- where i may be either 'A', 'B', ..., 'H' for the various Channels.

See the section on I/O for more details. (Index)



RCHi
'Reset and Load Channel'+0540 (for Channel 'A')
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

The Channel ('A' - 'H') must be specified. The 'RCHi' instruction must be executed immediately following a Read Select or Write Select instruction in order for I/O to initiate. (Index)



RCT
'Restore Channel Traps'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

Details not Known (Index)



RDCi
'Reset data Channel'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may change operation [TAG]Indirection: No
Description:

Resets the specified Channel after hang-up.

See the section on I/O for more details. (Index)



RDS
'Read Select'+0762
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Causes the machine to prepare to read information using the channel and an I/O device that is specified in the Y-address. A Reset and Load Channel instruction must follow within a specified time or the I/O unit will be disconnected and a record passed over. No other Select instruction should be given in between.

The code in the Y-address specifies the channel, I/O unit (tape, reader, punch, printer, etc.) and for tape and printer designate whether the mode of operation is binary or binary coded decimal. In the case of tapes, where as many as ten tape units may be attached to the channel, the code indicates which tape number is to be used.

See the section on I/O for more details. (Index)



REWi
'Rewind Tape'+0772
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Rewind the specified tape to the load point. The tape must be designated ('A' - 'H') and is in the Y-field of the instruction. (Index)



RFT
'Right Half Indicators OFF Test'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: Details not Known

(Index)



RIA
'Reset Indicators from Accumulator'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- c(AC)

The contents of the Sense Indicator Register are replaced with the c(AC). (Index)



RICi
'Reset Channel i'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

(Index)



RIL
'Reset Indicators of Left Half'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- Binary Zeros [Left Half Only]

The left half of the Sense Indicator Register is loaded with binary zeros. (Index)



RIR
'Reset Indicators of Right Half'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- Binary Zeros (Right Half Only]

The right-half of the Sense Indicator Register is cleared to binary zeros. (Index)



RIS
'Reset Indicators from Storage'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IR) <- (Y)

The contents of the Sense Indicator Register is replaced with the contents of the effective address (Y). (Index)



RND
'Round'+0760 0010
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23][OP CODE: 24-35]
Indexing: NoIndirection: No
Description: c(AC) <- c(AC) or c(AC) + 1

The Rounding instruction is most used after division operations. If the results of multiplication are to be rounded, the 'Multiply and Round' instruction can be used. If position 1 of the MQ contains a 1-bit, then the c(AC) are incremented by 1. If position 1 of the MQ contains a zero, then the AC remains unchanged. In either case, the contents of MQ are not changed. Overflow of the AC is possible, so 'RND' should be followed by a test for overflow. (Index)



RNT
'Right Half Indicators ON Test'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17]] [R: 18-35]
Indexing: NoIndirection: No
Description: Details not Known

(Index)



RPRi
'Read Printer, Channel i'+0762
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

Prepare to read from the printer connected to the Channel specified by i where i = 'A',..., 'H'.

See the section on I/O for more details. (Index)



RQL
'Rotate MQ Left'-0773
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(MQ) <- c(MQ) [Rotated Left]

The c(MQ) are shifted left Y bit positions in an "end around" fashion whereby bits shifted out of the sign bit reappear in position 35. No bits are lost. (Index)



RSCi
'Reset and Start Channel i'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details not Known (Index)



RTBi
'Read Select Tape Unit j attached to Channel i+0762
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Read select the tape unit number specified by j that is attached to channel i where i may be either 'A', 'B',..., 'H' to designate the various channels.

See the section on I/O for more details. (Index)



RTDi
'Read Tape Decimal'+0762
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

The Channel ('A' - 'H') must be specified (e.g., 'RTDA'). When followed by an 'RCH' instruction, 'RTDi' causes the machine to read one record into core storage from the tape drive that is specified in the Y-field. The Channel must also be specified in the Y-field and the tape density must be compatible otherwise both detectable and undetectable errors will occur. (Index)



RUNi
'Rewind and Unload Tape'-0772
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Rewind the specified tape to the load point and automatically set it to unload. The tape must be specified ('A' - 'H' e.g., 'RUNA') and resides in the Y-field. (Index)



SBM
'Subtract Magnitude'-0400
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) - c(Y)

The c(AC) are replaced with the c(Y) subtracted algebraically from the c(AC). (Index)



SCA
'Store Complement of Index in Address'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(Y) <- c(XR) [2s Complement]

The 2s complement of the contents of the specified Index Register are stored into the (Y), bits 21-35. (Index)



SCD
'Store Complement of Index in Decrement'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(Y) <- c(XR) [2s complement, bits 3-17]

The contents of the decrement field, bits 3-17, of the c(Y), are replaced with the 2s complement of the contents of the specified Index Register. (Index)



SCHi
'Store Channel'+0640
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Stores the contents of the Data Channel Register associated with the specified Channel i where i may be either 'A', 'B', ..., 'H' into a specified memory location.

See the section on I/O for more details. (Index)



SDHi
'Set Density High, Channel i (SDN)'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Allows Program Control of Tape Density. See the section on I/O for more details. (Index)



SDLi
'Set Density Low, Channel i (SDN)'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Allows Program Control of Tape Density. See the section on I/O for more details. (Index)



SIL
'Set Indicators of Left Half'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- Binary Ones [Left Half Only]

The left-half of the Sense Indicator is loaded with binary ones. (Index)



SIR
'Set Indicators of Right Half'+????
Type D: [OP CODE: S, 1-11] [Unused: 12-17] [R: 18-35]
Indexing: NoIndirection: No
Description: c(Sense Indicator) <- Binary Ones [Right Half Only]

The right-half of the Sense Indicator is loaded with binary ones. (Index)



SLF
'Sense Lights Off'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [LIGHT: 24-35]
Indexing: Yes -- But may change the operation [TAG]Indirection: No
Description: Turns OFF all of the Sense Lights.

(Index)



SLN
'Sense Light On'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [LIGHT: 24-35]
Indexing: Yes -- But may change the operation [TAG]Indirection: No
Description: c(Sense Lights) [Turned ON]

The instruction turns ON the Sense Light specified in the LIGHT field of the instruction word. (Index)



SLQ
'Store Left Half MQ'-0620
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(MQ)

The c(MQ), bits S, 1-17, replace the corresponding bits of the c(Y). (Index)



SLT
'Test Sense Light'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [LIGHT: 24-35]
Indexing: Yes -- But may change the operation [TAG]Indirection: No
Description: Tests whether the Sense Light, specified by the contents of the LIGHT field in the instruction word, is ON or OFF. If the Sense Light is ON, then it is turned OFF and the machine skips one instruction. If the Light is OFF, then the machine executes the next sequential instruction.

(Index)



SLW
'Store Logical Word'+0602
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(AC)

The contents of (Y) are replaced with the c(AC). The sign position in c(Y) is replaced with the P position of the AC. The instruction is identical to 'STO' with exception of the sign. (Index)



SPRi
'Sense Printer, Channel i'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change of operation [TAG]Indirection: No
Description:

Details not Known (Index)



SPTi
'Sense Printer Test, Channel i'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

(Index)



SPUi
'Sense Punch, Channel i'+????
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: Yes - but may cause change in operation [TAG]Indirection: No
Description:

(Index)



SSM
'Set Sign Minus'+0760/3
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: NoIndirection: No
Description: c(AC) <- c(AC) [Sign Bit set Negative]

The Sign bit in the c(AC) is set Negative. (Index)



SSP
'Set Sign Plus'+0760/3
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [Y: 24-35]
Indexing: NoIndirection: No
Description:c(AC) <- c(AC) [Sign Bit set Positive]

The Sign-bit of the c(AC) is set to Positive. (Index)



STA
'Store Address'+0621
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(AC) [Positions 21-35 only]

The c(AC), positions 21-35, replace the c(Y), positions 21-35. The c(Y), positions S, 1-20, and the c(AC) remain unchanged. (Index)



STCi
'Start Channel i'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

Details not Known (Index)



STD
'Store Decrement'+0622
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(AC) [Positions 3-17 only]

The c(AC), positions 3-17, replace the c(Y), positions 3-17. The c(Y), positions S, 1-2, 18-35, and the c(AC) remain unchanged. (Index)



STI
'Store Indicators'+0604
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(SIR)

The contents of the Sense Indicator Register replaces the c(Y). The c(SIR) remain unchanged. (Index)



STL
'Store Instruction Location Counter'-0625
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(IC) + 1

The location of the next instruction is stored into the c(Y), bits 21-35. (Index)



STO
"Store"+0601
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(AC)

The c(AC) replace the c(Y). The sign and bits 1-35 of the AC move into the storage location specified by (Y). The c(AC) remains unchanged. (Index)



STP
'Store Prefix'+0630
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(AC) [Positions P/S, 1-2 only]

The c(AC), positions P, 1-2, replace the c(Y), positions S, 1-2. The c(Y), positions 3-35, and the c(AC) remain unchanged. (Index)



STQ
"Store from MQ Register"-0600
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(MQ)

The c(MQ) replace the c(Y). The bits in the MQ move into the storage location specified by (Y) and the c(MQ) remain unchanged. (Index)



STR
'Store Location and Trap'-1
Type A: [S, 1-2] [D: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c(IC) <- 0002

The Instruction Location Counter contents (the current instruction address plus one) are stored in location 0000, bits 21-35. The machine then automatically transfers to address 0002. The 'STR' instruction only uses the bits S, 1-2 of the instruction word. (Index)



STT
'Store TAG'+0625
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- c(AC) [Positions 18-20 only]

The c(AC), positions 18-20, replace the c(Y), positions 18-20. The c(Y), positions S, 1-17, 21-35, and the c(AC) remain unchanged. (Index)



STZ
'Store Zero'+0600
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(Y) <- 0

The c(Y) are replaced with zero. The sign bit of the (Y) address is set to positive. (Index)



SUB
"Subtract"+0402
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC) <- c(AC) - c(Y)

The c(Y) are algebraically subtracted from the c(AC). The difference replaces the c(AC) and the c(Y) remain unchanged. (Index)



SWT
'Sense Switch Test'+0760
Type E: [OP CODE: S, 1-11] [Unused: 12-17] [TAG: 18-20] [Unused: 21-23] [SWITCH: 24-35]
Indexing: Yes -- However, indexing may change the instruction [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

The instruction tests whether the Sense Switch, specified in the SWITCH portion, bits 24-35, of the instruction word (where the contents are 1, 2, 3, 4, 5, or 6) is ON or OFF. if the specified sense switch is ON, then the machine skips one instruction. If the switch is OFF, then the machine executes the next sequential instruction. (Index)



SXA
'Store Index in Address'+0634
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(Y) <- c(XR)

The contents of the specified Index Register replace the c(Y), bits 21-35. The c(Y), bits S, 1-20, are not changed. (Index)



SXD
'Store Index in Decrement'-0634
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(Y) <- c(XR)

The contents of the specified Index Register replace the c(Y), bits 3-17. The c(Y), bits S, 1-2, 18-35, are not changed. (Index)



TCNi
'Transfer on Channel i Not in Operation'-006i (i = 0,..., 6)
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

If the specified Channel is not busy, then the machine executes the instruction specified by the Y-field. If the Channel is active, then the machine executes the next sequential instruction. The Channel must be specified ('A' - 'H', e.g., 'TCOA') (Index)



TCOi
'Transfer If Channel in Operation'+006i (i = 0,..., 6)
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

If the specified Channel is busy, then the machine executes the instruction specified by the Y-field. If the Channel is free, then the machine executes the next sequential instruction. The Channel must be specified ('A' - 'H', e.g., 'TCOA') (Index)



TEFi
'Transfer on End-of-File'+0030
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

In the event that an end of file gap is reached while reading tape, an indicator is automatically turned on. If the indicator is ON, then the 'TEFi' instruction turns the indicator OFF and the machine transfers to the instruction specified in the Y-field. If the indicator is OFF, then the 'TEFi' instruction causes the machine to execute the next sequential instruction. The Channel ('A' - 'H') must be specified (e.g., 'TEFA'). (Index)



TIF
'Transfer When Indicators Off'+0046
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(Y)

For each bit in the C(AC) that is a binary one, the corresponding bit in the Sense Indicator Register is checked. If all of the checked bits in the Sense Indicator Register are binary zeros, then the machine transfers to the address specified by (Y). Otherwise, the machine executes the next sequential instruction. (Index)



TIO
'Transfer When Indicators On'+0042
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(Y)

For each bit in the C(AC) that is a binary one, the corresponding bit in the Sense Indicator Register is checked. If all of the checked bits in the Sense Indicator Register are binary ones, then the machine transfers to the address specified by (Y). Otherwise, the machine executes the next sequential instruction. (Index)



TIX
'Transfer on Index'+2000
Type A: [OP: S, 1-2] [DECREMENT: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: (c(XR) <- c(XR) - DECREMENT and c(IC) <- (Y)) or (c(IC) <- c(IC) + 1)

If the contents of the specified Index Register (TAG) are greater than the DECREMENT field of the instruction, positions 3-17, then the contents of the specified Index Register are reduced by the DECREMENT and the machine transfers to the address specified by Y. If the contents of the specified Index Register (TAG) are less than or equal to the DECREMENT field of the instruction, positions 3-17, then the machine executes the next sequential instruction and the contents of the Index Register are not modified. (Index)



TLQ
'Transfer on Low MQ'+0040
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

If the c(MQ) are algebraically less than the c(AC), then the machine transfers to the address specified in the Y field of the instruction. If the c(MQ) are algebraically greater than or equal to the c(AC), then the machine executes the next sequential instruction. (Index)



TMI
'Transfer on Minus'-0120
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(Y) or c(IC) + 1

If the sign position of the AC is negative (binary one), then the machine will transfer to the location specified by c(Y). If the sign position of the AC is positive (binary zero), then the machine will execute the next sequential instruction. (Index)



TNO
'Transfer on No Overflow'-0140
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:c(IC) <- c(IC) + 1 or (Y)

If the AC Overflow Indicator is OFF, then the 'TNO' instruction causes the machine to transfer to (Y). If the AC Overflow Indicator is ON, then the 'TNO' instruction turns the indicator OFF and the machine executes the next sequential instruction. (Index)



TNX
'Transfer on No Index'-2
Type A: [OP CODE: S, 1-2] [D: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- Y or c(IC) + 1

If the contents of the specified Index Register are less than or equal to the contents of the DECREMENT field, bits 3-17, of the instruction word, then the machine transfers to the address contained in the Y field, bits 21-35, of the instruction word. If the contents of the specified Index Register are greater than the contents of the DECREMENT field, then the contents of the specified Index Register is reduced by the number in the DECREMENT field and the machine executes the next sequential instruction. (Index)



TNZ
'Transfer on No Zero'-0100
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

If the c(AC), bits Q, P, 1-35, are not zero, then the machine transfers to the address specified by Y. If the fields are zero, then the machine executes the next sequential instruction. (Index)



TOV
"Transfer on Overflow"+0140
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- either (Y) or c(IC) + 1

In addition and subtraction, if an overflow occurs, then the AC Overflow Indicator will be illuminated on the control console. TOV tests the indicator and if it is ON, then it will be turned OFF and the processor will transfer to the address specified by (Y). If the indicator is OFF, then the processor will execute the next sequential instruction. (Index)



TPL
'Transfer on Plus'+0120
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(Y) or c(IC) + 1

If the sign position of the AC is positive (binary zero), then the machine transfers to the location specified by c(Y). If the sign is negative (binary one), then the machine executes the next sequential instruction. (Index)



TQO
'Transfer on MQ Overflow'+????
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

Details Not Known (Index)



TQP
'Transfer on MQ Plus'+0162
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

if the sign bit of the c(MQ) is positive, then the machine executes the instruction at (Y) otherwise the machine executes the next sequential instruction. In a comparison, +0 is greater than -0. (Index)



TRA
'Transfer'+0020
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- (Y)

The machine transfers to the instruction specified in the (Y) address portion of the instruction. (Index)



TRCi
'Transfer on Redundancy'+0022
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or (Y)

The Channel ('A'- 'H') must be specified (e.g., 'TRCA'). In the event than an I/O parity check ever occurs, then the parity indicator is automatically illuminated on the control console. If the indicator is ON, then 'TRCi' turns it OFF and the machine transfers to the instruction specified in the Y-field. If the indicator is OFF, then the machine executes the next sequential instruction. (Index)



TSX
'Transfer and Set Index'+0074
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(XR) <- c(IC) (Two's Complement]. c(IC) <- (Y)

The two's complement of the current c(IC) replace the contents of the specified Index Register and the machine transfers to (Y). The instruction is primarily used for subroutine linkage. (Index)



TTR
'Trap Transfer'+0021
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(Y)

Causes the machine to transfer to location (Y) even when in the Transfer Trapping Mode (see the 'ETM' (Enter Trapping Mode) instruction for a complete description of the Transfer Trapping Mode). The 'TTR' instruction makes it possible to have a normal transfer even when in the Transfer Trapping Mode and is the only transfer instruction that will not cause an automatic jump to location 0001. (Index)



TXH
'Transfer on Index High'+3000
Type A: [OP: S, 1-2] [DECREMENT: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or (Y)

If the contents of the specified Index Register (TAG) are greater than the DECREMENT field, positions 3-17, of the instruction, then the machine transfers to the location specified in Y. Otherwise, the machine executes the next sequential instruction. (Index)



TXI
'Transfer with Index Incremented'+1000
Type A: [OP: S, 1-2] [DECREMENT: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(XR) <- c(XR) + DECREMENT [Positions 3-17] and c(IC) <- Y

The DECREMENT field of the instruction, positions 3-17, are added to the contents of the specified Index Register (TAG) and the sum replaces the contents of the specified Index Register. The machine then transfers to the address specified by the Y field, positions 21-35, of the instruction. (Index)



TXL
'Transfer on Index Low or Equal'-3000
Type A: [OP: S, 1-2] [DECREMENT: 3-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(IC) <- c(IC) + 1 or (Y)

If the contents of the specified Index Register (TAG) are less than or equal to the DECREMENT field, positions 3-17, of the instruction, then the machine transfers to (Y). Otherwise, the machine executes the next sequential instruction. (Index)



TZE
"Transfer on Zero"+0100
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- either (Y) or c(IC) + 1

If the c(AC) are zero, then the processor will transfer to the location specified by (Y). If the c(AC) are not zero, then the next sequential instruction will be executed. (Index)



UAM
'Unnormalized Add Magnitude'-0304
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) + c(Y)

The absolute value of the floating point number in the c(Y) are added to the floating point number in the c(AC) and the unnormalized floating point result is placed into the c(AC and MQ).

The scaling of the unnormalized floating point result is still correct but there may be leading zeros in the fraction. (Index)



UFA
'Unnormalized Floating Add'-0300
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) + c(Y)

The floating point number in the c(AC) are added to the floating point number in the c(Y) and the unnormalized floating point result is placed into the c(AC and MQ).

The scaling of the unnormalized result is correct but there may be leading zeros in the fraction. (Index)



UFM
'Unnormalized Floating Multiply'-0260
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(MQ) * c(Y)

The floating point number in the c(MQ) is multiplied by the floating point number in the c(Y) and the unnormalized floating point result is placed into the c(AC and MQ) with the exponent and the most significant portion of the fraction in the c(AC) and the least significant portion of the fraction in the c(MQ).

The scaling of the unnormalized floating point result is correct but there may be leading zeros in the fraction. (Index)



UFS
'Unnormalized Floating Subtract'-0300
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) - c(Y)

The floating point number in the c(Y) are subtracted from the floating point number in the c(AC) and the unnormalized result is placed in the c(AC and MQ) with the most significant portion of the fraction in the c(AC).

The scaling of the unnormalized floating point result is correct but there may be leading zeros in the fraction. (Index)



USM
'Unnormalized Floating Subtract Magnitude'-0306
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(AC and MQ) <- c(AC) - c(Y)

The absolute value of the floating point number in the c(Y) are subtracted from the floating point number in the c(AC) and the unnormalized floating point result is placed into the c(AC and MQ) with the most significant portion of the fraction in the c(AC).

The scaling of the unnormalized floating point result is correct but there may be leading zeros in the fraction. (Index)



VDH
'Variable Length Divide or Halt'+0224
Type C: [OP CODE: S, 1-9] [C: 10-17] [Tag: 18-19] [20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(AC and MQ) <- c(AC and MQ) / c(Y)

The 'DVH' and 'DVP' instructions use all 35 bits of the divisor and dividend to produce a 35-bit result and 35-bit remainder. However, the 'VDH' instruction allows specification of the number of bits to develop in the quotient.

The specified bits in the result occupy the right-hand (low order) positions of the MQ register and the remainder occupies the AC register and the rest of the MQ register. The count is specified in the Count field (10-17) of the instruction. In the event that the divisor is less in magnitude than the dividend, then the machine halts. (Index)



VDP
'Variable Length Divide or Proceed'+0225
Type C: [OP CODE: S, 1-9] [C: 10-17] [Tag: 18-19] [20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(AC and MQ) <- c(AC and MQ) / c(Y)

The 'DVH' and 'DVP' instructions use all 35 bits of the divisor and dividend to produce a 35-bit result and 35-bit remainder. However, the 'VDP' instruction allows specification of the number of bits to develop in the quotient.

The specified bits in the result occupy the right-hand (low order) positions of the MQ register and the remainder occupies the AC register and the rest of the MQ register. The count is specified in the Count field (10-17) of the instruction. In the event that the divisor is less in magnitude than the dividend, then the machine does not halt but rather continues with the next instruction. (Index)



VLM
'Variable Length Multiply'+0204
Type C: [OP CODE: S, 1-9] [C: 10-17] [Tag: 18-19] [20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description: c(AC and MQ) <- c(Y) * c(MQ)

The 'MPY' and 'MPR' instructions use all 35 bits of the multiplier and the multiplicand to produce a 70-bit result. The 'VLM' instruction specifies the number of bits of the multiplier (in MQ) which are to be used. All 35 bits of the multiplicand are still used. Reducing the size of the multiplier increases the speed of the multiplication process.

The 'VLM' instruction uses the Count field (C) to indicate the number of bits of the multiplier to be used. (Index)



WEFi
'Write End of File'+0770
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Write an end-of-file gap and tape mark to the specified tape drive. The Channel ('A' - 'H') must be specified (e.g., 'WEFA'). (Index)



WPBi
'Write Printer Binary, Channel i'+0766
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

Prepare to write to the printer connected to the specified Channel (i = 'A',... , 'H').

See the section on I/O for more details. (Index)



WPDi
'Write Select Printer on Channel i'+0766
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Write selects the printer in decimal mode on channel i where i may be either 'A', 'B', ..., 'H' to designate the various channels.

See the section on I/O for more details. (Index)



WPUi
'Write Punch, Channel i'+0766
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

Prepare to write to the punch connected to the Channel specified by i where i = 'A',..., 'H'.

See the section on I/O for more details. (Index)



WRS
'Write Select'+0766
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

Causes the machine to prepare to write information using the channel and an I/O device that is specified in the Y-address. A Reset and Load Channel instruction must follow within a specified time or the I/O unit will be disconnected and a record passed over. No other Select instruction should be given in between.

The code in the Y-address specifies the channel, I/O unit (tape, reader, punch, printer, etc.) and for tape and printer designate whether the mode of operation is binary or binary coded decimal. In the case of tapes, where as many as ten tape units may be attached to the channel, the code indicates which tape number is to be used.

See the section on I/O for more details. (Index)



WTBi
'Write Tape Binary, Channel i'+0766
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description:

Prepare to write to a tape drive connected to the specified Channel by i where i = 'A',..., 'H'.

See the section on I/O for more details. (Index)



WTDi
'Write Tape Decimal'+0766
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: No
Description:

The Channel ('A' - 'H') must be specified. When used with the 'RCH' instruction, 'WTD' writes a record, from a buffer in core memory, to the specified tape. If 'WTD' is used without an accompanying 'RCH', then a 3.75-inch piece of blank tape is written which can be used to jump over a bad spot on the tape. (Index)



XCA
'Exchange AC and MQ'+0131
Type D: [OP CODE: S, 1-11] [Unused: 12-35]]
Indexing: NoIndirection: No
Description: c(AC) <-> c(MQ)

The c(AC) and the c(MQ) are exchanged. Positions P and Q in the AC are cleared. (Index)



XCL
'Exchange Logical AC and MQ'-0130
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: NoIndirection: No
Description: c(AC) <=> c(MQ)

The c(AC), bits P, 1-35, are exchanged with the c(MQ). The S and Q bits of the AC are cleared. (Index)



XEC
'Execute'+0522
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description:

The instruction at (Y) is executed and the machine then executes the next sequential instruction after the 'XEQ' instruction unless the instruction executed caused a transfer of control. (Index)



ZET
'Storage Zero Test'+0520
Type B: [OP CODE: S, 1-11] [IA: 12-13] [Unused: 14-17] [TAG: 18-20] [Y: 21-35]
Indexing: Yes [TAG]Indirection: Yes [IA]
Description: c(IC) <- c(IC) + 1 or c(IC) + 2

If the c(Y) are zero, then the machine will skip one instruction. If the c(Y) are non-zero, then the machine will execute the next sequential instruction. The c(Y) are not changed. (Index)



http://www.frobenius.com/instruction-set.htm -- Last Revision: 23 August 2001
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